hardware - Translating a VHDL monitor into a PSL assertion -

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I have an interesting question about the PSL claim. Here is a VHDL monitor process. This is a process which is dedicated to an accused, and thus is a non-synthesisable, this monitor examines the existing FSM state and stores the value of two registers: " Input 1 "And" reg136 ". Finally, it starts the " emphasis " statement to compare the prices of these registers. 

  process (clk) variable var_a: signed (7 down down to 0); Variable var_b: signed (7 down 0); If it is starting (rising_ege (CLK)) then the case happens when s0 = & gt; Var_a: = signed (input 1); When s22 = & gt; Var_t34: = signed (reg136); When s85 = & gt; By emphasis (var_t34 & lt; var_a) report "Apprehension XXX failed: (t34

The question is: Is there a way to translate the monitor into a PSL (Property Specification Language) claim?

Important : Registers "Input 1" and "Reg 136" can be read only when FSM State is on SK and S22, respectively. Otherwise, the data contained in these registers is not related to the specified variable "A" and "T34", as a result, a PSL statement should have a way to read and store the values ​​of the correct FSM states.

Thank you!

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