gcc - Prepending (w/out newlines) to an auto-generated dependency list for Makefiles -

Not sure if the title is understandable ... then I'll extend a bit.

I is being won by this makefile which uses the GCC's auto-dependency list generator.

At the same time, I wanted to have a well-sorted directory structure that separates the source, headers and resources.

Dependency

< / Li>

Now, makefile dependency list generator ATM is:

  $ (DEP_PATH)%. D: $ (SRC_PATH)% C @ $ {CC} $ (CFLAGS) -MMKK $ (Include) $ & lt; & Gt; $ {DEP_PATH} $$ D $ $ @  

The idea involved is that we make dependency rules, then include it in the making of the building.

And the result to say, foo1.o is:

  foo1.o: src / foo1.c included / include foo1.h / foo2.h included / foo3 .h  

This will work fine if I find all of my items in the main directory ... even when they say instead of / main / objects ... / Main / items / foo1.o

Now, I tried to do this:

  @echo "$ (OBJ_PATH)" & gt; $ (DEP_PATH) $ * D $$ {CC} $ (CFLAGS) -MMKK $ (Include) $ & lt; & Gt; & Gt; $ (DEP_PATH) $ * D  

which feeds the object path of the new / overlapping file, then adds the GCC auto-dependency rule build for it ... but it adds between two sets new line.

I said that trying to cate two different files with information ... but they also get new lines.

Is there a good way to add new lines to W / O Dependency File?

Also, if there is any good tutorial on makefile, cat and echo, I would appreciate it.

Thanks for any and all responses.

The answer you asked is sed :

< Pre> @ $ {CC} blah blah | Sed 's | ^ | $ (OBJ_PATH) | ' & Gt; $ (DEP_PATH) $ * D

but you will have a different problem with this part:

  include $ $  

Include instructions for yourself, this is not a shell command (such as $ (CC) ... ). And $ @ is an automatic variable, which is defined within the rule, is not available for instructions outside of the rule. Instead, do something like this:

  $$ (DEP_PATH) / *. D  

and see.